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CY7C182
8Kx9 Static RAM
Features
* High speed -- tAA = 25 ns * x9 organization is ideal for cache memory applications * CMOS for optimum speed/power * Low active power -- 770 mW * Low standby power -- 195 mW * TTL-compatible inputs and outputs * Automatic power-down when deselected * Easy memory expansion with CE1, CE2, OE options The CY7C182, which is oriented toward cache memory applications, features fully static operation requiring no external clocks or timing strobes. The automatic power-down feature reduces the power consumption by more than 70% when the circuit is deselected. Easy memory expansion is provided by an active-LOW Chip Enable (CE1), an active HIGH Chip Enable (CE2), an active-LOW Output Enable (OE), and threestate drivers. An active-LOW Write Enable signal (WE) controls the writing/reading operation of the memory. When CE1 and WE inputs are both LOW, data on the nine data input/output pins (I/O0 through I/O8) is written into the memory location addressed by the address present on the address pins (A0 through A12). Reading the device is accomplished by selecting the device and enabling the outputs, (CE1 and OE active LOW and CE2 active HIGH), while (WE) remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins is present on the nine data input/output pins. The input/output pins remain in a high-impedance state unless the chip is selected, outputs are enabled, and write enable (WE) is HIGH. A die coat is used to insure alpha immunity.
Functional Description
The CY7C182 is a high-speed CMOS static RAM organized as 8,192 by 9 bits and it is manufactured using Cypress's highperformance CMOS technology. Access times as fast as 25 ns are available with maximum power consumption of only 770 mW.
Logic Block Diagram
Pin Configuration
DIP/SOJ Top View
A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 V CC WE CE 2 A3 A2 A1 OE A0 CE 1 I/O 8 I/O 7 I/O 6 I/O 5 I/O 4
I/O0 INPUT BUFFER A1 A2 A3 A4 A5 A6 A7 A8 ROW DECODER I/O1 SENSE AMPS I/O2 I/O3 I/O4 I/O5 I/O6
CE1 CE2 WE OE
A5 A6 A7 A8 A9 A 10 A 11 A 12 I/O 0 I/O 1 I/O 2 I/O 3 GND
256 x 32 x 9 ARRAY
COLUMN DECODER A10 A11 A12 A0 A9
POWER DOWN
I/O7 I/O8
C182-1
C182-2
Selection Guide
7C182-25 Maximum Access Time (ns) Maximum Operating Current (mA) Maximum Standby Current (mA) 25 140 35 7C182-35 35 140 35 7C182-45 45 140 35
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134
*
408-943-2600 October 4, 1999
CY7C182
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .....................................-65C to +150C Ambient Temperature with Power Applied ..................................................-55C to +125C Supply Voltage to Ground Potential[1] ..............-0.5V to +7.0V DC Voltage Applied to Outputs in High Z State[1] .................................................-0.5V to +7.0V DC Input Voltage[1] ..............................................-0.5V to +7.0V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015.2) Latch-Up Current .................................................... >200 mA
Operating Range
Range Commercial Ambient Temperature 0C to + 70C VCC 5V 10%
Electrical Characteristics Over the Operating Range
7C182-25, 35, 45 Parameter VOH VOL VIH VIL IIX Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[1] Input Load Current GND < VIN < VCC, GND < VOUT < VCC, Output Disabled VCC = Max., VOUT = GND VCC = Max., VOUT = GND VCC Max., Output Current = 0 mA, f = Max., V IN = VCC or GND Max V CC, CE1 > VIH, CE2 < VIL, VIN > VIH or VIN < VIL, f = fMAX Max V CC, CE1 > VCC - 0.3V, CE2 < 0.3V, VIN > VCC - 0.3V or VIN < 0.3V, f = 0 Test Conditions VCC Min., IOH = -4.0 mA. VCC Min., IOL = 8.0 mA 2.2 -0.5 -10 Min. 2.4 0.4 VCC 0.8 +10 Max. Unit V V V V A
IOZ IOS ICC
Output Leakage Current Output Short Circuit Current[2] VCC Operating Circuit Current Automatic Power-Down Current -- TTL Inputs Automatic Power-Down Current -- CMOS Inputs
-10
+10 -300 140 35 20
A mA mA mA mA
Capacitance[3]
Parameter COUT CIN
Note: 1. 2. 3. VIL (min.) = -3.0V for pulse durations of less than 20 ns. Duration of the short circuit should not exceed 30 seconds. Not more than one output should be shorted at one time. Tested initially and after any design or process changes that may affect these parameters.
Description Output Capacitance Input Capacitance
Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V
Max. 10 10
Unit pF pF
AC Test Loads and Waveforms
R1 481 5V OUTPUT 30 pF INCLUDING JIG AND SCOPE R2 255 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE R2 255
C182-3
R1 481 3.0V GND 10% ALL INPUT PULSES 90% 90% 10% < 5 ns
C182-4
< 5 ns
(a)
Equivalent to: THEVENIN EQUIVALENT 167 OUTPUT 1.73V
(b)
2
CY7C182
Switching Characteristics Over the Operating Range
7C182-25 Parameter READ CYCLE tRC tAA tOHA tACE1 tACE2 tLZCE1 tLZCE2 tHZCE1 tHZCE2 tPU tPD tDOE tLZOE tHZOE WRITE CYCLE[6] tWC tSA tAW tSD tSCE1 tSCE2 tPWE tHA tHD tLZWE tHZWE Write Cycle Time Address Set-Up Time Address Valid to End of Write Data Set-Up Time CE1 LOW to Write End CE2 HIGH to Write End WE Pulse Width Address Hold from End of Write Data Hold Time Write HIGH to Low Z Write LOW to High Z
[7] [5, 7, 8] [4]
7C182-35 Min. 35 Max.
7C182-45 Min. 45 Max. Unit ns 45 3 45 45 5 5 ns ns ns ns ns ns 25 25 0 ns 25 20 3 25 45 0 40 25 40 40 30 0 0 3 ns ns ns ns ns ns ns ns ns ns ns ns ns ns 20 ns ns
Description Read Cycle Time Address to Data Valid Data Hold from Address Change CE1 Access Time CE2 Access Time CE1 LOW to Low Z CE2 HIGH to Low Z CE1 HIGH to High Z CE2 LOW to High Z
[5] [5]
Min. 25
Max.
25 3 25 25 5 5 18 18 0 20 18 3 3 18 25 0 20 15 20 20 20 0 0 3 13 35 0 30 20 30 30 25 0 0 3 0 5 5 3
35 35 35
20 20 20 20 20
CE1 LOW to Power-Up CE1 HIGH to Power-Down OE Access Time OE LOW to Low Z OE HIGH to High Z
[5]
15
Notes: 4. WE is HIGH for read cycle. 5. t HZCE and t HZWE are specified with CL = 5 pF. Transition is measured 500 mV from steady-state voltage. 6. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, and WE LOW. All three signals must be asserted to initiate a write and any signal can terminate a write by being deasserted. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 7. At any given temperature and voltage condition, tLZWE is less than t HZWE for any given device. These parameters are sampled and not 100% tested. 8. Address valid prior to or coincident with CE transition LOW and CE2 transition HIGH.
3
CY7C182
Switching Waveforms
Read Cycle
ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID
C182-5
No. 1[4, 9]
tRC
Read Cycle No. 2
CE1
[4, 10]
tRC
CE2 OE OE
tACE1 tACE2 tHZOE tHZCE DATA VALID tPD ICC 50% 50% ISB
C182-6
tDOE tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU
HIGH IMPEDANCE
DATA OUT
Write Cycle No. 1 (WE Controlled)
ADDRESS
[6]
tWC
CS1
tSCE1 tSCE2
CS2 tAW WE tSA tPWE tHA
tSD DATA IN tHZWE DATA I/O DATA UNDEFINED DATA VALID
tHD
tLZWE HIGH IMPEDANCE
C182-7
Notes: 9. Device is continuously selected. OE, CE1 = VIL. CE2 = VIH. 10. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE HIGH, the output remains in a high-impedance state.
4
CY7C182
Switching Waveforms (continued)
Write Cycle No. 2 (CE Controlled)
[6, 10]
tWC ADDRESS CE1 tSCE1 tSCE2
tSA
CE2
tAW tPWE
tHA
WE tSD DATA IN tHZWE DATA I/O HIGH IMPEDANCE DATA UNDEFINED
C182-8
tHD DATA VALID
Truth Table
CE1 H L L L X CE2 X H H H L OE X L X H X WE X H L H X Data In Z Z Valid Z Z Data Out Z Valid Z Z Z Read Write Output Disable Deselect Mode Deselect/Power-Down
Ordering Information
Speed (ns) 25 35 45 Ordering Code CY7C182-25PC CY7C182-25VC CY7C182-35PC CY7C182-35VC CY7C182-45PC CY7C182-45VC Document #: 38-00110-F Package Name P21 V21 P21 V21 P21 V21 Package Type 28-Lead (300-Mil) Molded DIP 28-Lead Molded SOJ 28-Lead (300-Mil) Molded DIP 28-Lead Molded SOJ 28-Lead (300-Mil) Molded DIP 28-Lead Molded SOJ Commercial Commercial Operating Range Commercial
5
CY7C182
Package Diagrams
28-Lead (300-Mil) Molded DIP P21
51-85014-B
28-Lead (300-Mil) Molded SOJ V21
51-85031-B
(c) Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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